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This module integrates the USB transceivers with a 3. In the idle mode the CPU is frozen while the timers, the serial ports and the interrupt system are still operating. In the power-down mode the RAM is saved, the peripheral clock is frozen, but the device has full wake-up capability through USB events or external interrupts.
Alternate function of Port 1 2. Alternate function of Port 3 3. Alternate function of Port 4. Pinout Description 3. Table Keypad Interface Signal Description Type Description Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt if enabled. Alternate Function. The typical current of each output can be programmed by software to 2, 6 or 10 mA. Several outputs can be connected together to get higher drive capabilities.
Alternate Function P3. SCL input the serial clock from master. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. If an external oscillator is used, its output is connected to this pin.
If an external oscillator is used, leave XTAL2 unconnected. USB Data - signal Set to low level under reset. Alternate Function -. Control input for slave port read access cycles. Write Signal Write signal asserted during external data memory write operation. Control input for slave write access cycles. Reset Input Holding this pin low for 64 oscillator periods while the oscillator is running resets the device.
The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-up resistor which allows the device to be reset by connecting a capacitor between this pin and VSS. This pin is tied to 0 for at least 12 oscillator periods when an internal reset occurs hardware watchdog or power monitor.
This signal is active only when reading or writing external memory using MOVX instructions. External Access Enable EA I This pin must be held low to force the device to fetch code from external program memory starting at address h. Alternate Function P0 P2. Digital Ground VSS is used to supply the buffer ring and the digital core.
It is also used to power the on-chip voltage regulator of the Standard versions or the digital core of the Low Power versions. Typical Application 4.
The following figure represents the typical wiring schematic. Figure Typical Application. USB Pads Components must be close to the microcontroller Wires must be routed in Parallel and must be as short as possible.
Clock Controller 5. All the internal clocks to the peripherals and CPU core are generated by this controller. Value of capacitors and crystal characteristics are detailed in the section DC Characteristics. The X1 pin can also be used as input for an external 48 MHz clock. The clock controller outputs three different clocks as shown in Figure a clock for the CPU core a clock for the peripherals which is used to generate the Timers, PCA, WD, and Port sampling clocks a clock for the USB controller These clocks are enabled or disabled depending on the power reduction mode as detailed in Section Power Management, page Oscillator Block Diagram 2 0 1.
Figure shows the internal structure of the PLL. This block makes the comparison between the reference clock coming from the N divider and the reverse clock coming from the R divider and generates some pulses on the Up or Down signal depending on the edge position of the reverse clock. Value of the filter components are detailed in the Section DC Characteristics. It generates a square wave signal: the PLL clock. As soon as clock generation is enabled user must wait until the lock indicator is set to ensure the clock output is stable.
The typical divider values are shown in Table Registers Table When X2 is low, this bit has no effect. Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Do not set this bit. Clear to disable the PLL. Clear by hardware when PLL is unlocked. The table below shows all SFRs with their address and their reset value.
Dual Data Pointer Register The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location.
Use of Dual Pointer. Reserved The value read from this bit is indeterminate. This bit is a general-purpose user flag. Always cleared. Set to select DPTR1. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value.
In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Hardware programming mode is also available using specific programming tool. Fetching code constant from this location does not affect Ports 0 and 2. Figure shows the structure of the external address bus.
P0 carries address A while P2 carries address A Data D is multiplexed with A on P0. Table describes the external memory interface signals. Alternate Function P2. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in X2 mode.
For further information on X2 mode see the clock Section. For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information.
External Code Fetch Waveforms. The memory array user space 32 Kbytes 2. The Extra Row 3. The Hardware security bits 4. The column latch registers. It contains the users application code. The extra row contains information for bootloader usage see Software Registers on page 41 Hardware Security Space The hardware security space is a part of FM0 and has a size of 1 byte.
The 4 LSB can only be read by software and written by hardware in parallel mode. Column Latches The column latches, also part of FM0, have a size of full page bytes. The column latches are the entrance buffers of the three previous memory locations user array, XRow and Hardware security byte. A MOVC instruction is then used for reading these spaces. A specific sequence must be written in these bits to unlock the write protection and to launch the programming.
This sequence is 5 followed by A. Table summarizes the memory spaces to program according to FMOD bits. The Flash memory enters a busy state as soon as programming is launched. In this state, the memory is not available for fetching code. Thus to avoid any erratic execution during programming, the CPU enters Idle mode. Exit is automatically performed at the end of programming. Note: Interrupts that may occur during programming time must be disabled to avoid any spurious exit of the idle mode.
FBUSY is set when programming is in progress. Loading the Column Latches Any number of data from 1 byte to bytes can be loaded in the column latches.
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